//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2008-2013 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
// Version and Release Control Information:
//
// File Revision       : 149903
// File Date           :  2013-05-08 18:23:05 +0100 (Wed, 08 May 2013)
// Release Information : PL401-r0p1-00eac0
//------------------------------------------------------------------------------
// Purpose : HDL design file for AXI slave interface block
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//
//                               nic400_asib_vgalcd_mst_axi4.v
//                               =============
//
//------------------------------------------------------------------------------
//
//  Overview
// ==========
//
//   The Axi Slave Interface Block provides an interface between an external
//slave port on NIC400 and interconnect.
//
//   The ASIB can be configured to provide four modes of operation for each of
// the channels:
//    1. fully registered (total timing isolation between
//                         master and slave ports)
//    2. forward path registered only (timing isolation on data/ctrl/valid
//                                     paths only)
//    3. reverse path registered only (timing isolation on ready paths only)
//
//------------------------------------------------------------------------------


`include "nic400_asib_vgalcd_mst_axi4_defs_ysyx_rv32.v"

module nic400_asib_vgalcd_mst_axi4_ysyx_rv32
 (
  
    //vgalcd_mst_axi4_s AXI bus

    //AW Channel
    awid_vgalcd_mst_axi4_s,
    awaddr_vgalcd_mst_axi4_s,
    awlen_vgalcd_mst_axi4_s,
    awsize_vgalcd_mst_axi4_s,
    awburst_vgalcd_mst_axi4_s,
    awlock_vgalcd_mst_axi4_s,
    awcache_vgalcd_mst_axi4_s,
    awprot_vgalcd_mst_axi4_s,
    awvalid_vgalcd_mst_axi4_s,
    awready_vgalcd_mst_axi4_s,

    //W Channel
    wdata_vgalcd_mst_axi4_s,
    wstrb_vgalcd_mst_axi4_s,
    wlast_vgalcd_mst_axi4_s,
    wvalid_vgalcd_mst_axi4_s,
    wready_vgalcd_mst_axi4_s,

    //B Channel
    bid_vgalcd_mst_axi4_s,
    bresp_vgalcd_mst_axi4_s,
    bvalid_vgalcd_mst_axi4_s,
    bready_vgalcd_mst_axi4_s,

    //AR Channel
    arid_vgalcd_mst_axi4_s,
    araddr_vgalcd_mst_axi4_s,
    arlen_vgalcd_mst_axi4_s,
    arsize_vgalcd_mst_axi4_s,
    arburst_vgalcd_mst_axi4_s,
    arlock_vgalcd_mst_axi4_s,
    arcache_vgalcd_mst_axi4_s,
    arprot_vgalcd_mst_axi4_s,
    arvalid_vgalcd_mst_axi4_s,
    arready_vgalcd_mst_axi4_s,

    //R Channel
    rid_vgalcd_mst_axi4_s,
    rdata_vgalcd_mst_axi4_s,
    rresp_vgalcd_mst_axi4_s,
    rlast_vgalcd_mst_axi4_s,
    rvalid_vgalcd_mst_axi4_s,
    rready_vgalcd_mst_axi4_s,

    //vgalcd_mst_axi4_m AXI bus

    //AW Channel
    awid_vgalcd_mst_axi4_m,
    awaddr_vgalcd_mst_axi4_m,
    awlen_vgalcd_mst_axi4_m,
    awsize_vgalcd_mst_axi4_m,
    awburst_vgalcd_mst_axi4_m,
    awlock_vgalcd_mst_axi4_m,
    awcache_vgalcd_mst_axi4_m,
    awprot_vgalcd_mst_axi4_m,
    awvalid_vgalcd_mst_axi4_m,
    awvalid_vect_vgalcd_mst_axi4_m,
    awregion_vgalcd_mst_axi4_m,
    awready_vgalcd_mst_axi4_m,

    //W Channel
    wdata_vgalcd_mst_axi4_m,
    wstrb_vgalcd_mst_axi4_m,
    wlast_vgalcd_mst_axi4_m,
    wvalid_vgalcd_mst_axi4_m,
    wready_vgalcd_mst_axi4_m,

    //B Channel
    bid_vgalcd_mst_axi4_m,
    bresp_vgalcd_mst_axi4_m,
    bvalid_vgalcd_mst_axi4_m,
    bready_vgalcd_mst_axi4_m,

    //AR Channel
    arid_vgalcd_mst_axi4_m,
    araddr_vgalcd_mst_axi4_m,
    arlen_vgalcd_mst_axi4_m,
    arsize_vgalcd_mst_axi4_m,
    arburst_vgalcd_mst_axi4_m,
    arlock_vgalcd_mst_axi4_m,
    arcache_vgalcd_mst_axi4_m,
    arprot_vgalcd_mst_axi4_m,
    arvalid_vgalcd_mst_axi4_m,
    arvalid_vect_vgalcd_mst_axi4_m,
    arregion_vgalcd_mst_axi4_m,
    arready_vgalcd_mst_axi4_m,

    //R Channel
    rid_vgalcd_mst_axi4_m,
    rdata_vgalcd_mst_axi4_m,
    rresp_vgalcd_mst_axi4_m,
    rlast_vgalcd_mst_axi4_m,
    rvalid_vgalcd_mst_axi4_m,
    rready_vgalcd_mst_axi4_m,

    //Clock and reset signals
    aclk,
    aresetn

  );




  // ---------------------------------------------------------------------------
  //  Port definitions
  // ---------------------------------------------------------------------------
  
  //vgalcd_mst_axi4_s AXI bus


  //AW Channel
  input   [2:0]       awid_vgalcd_mst_axi4_s;              //write id of vgalcd_mst_axi4_s AXI bus AW channel
  input   [31:0]      awaddr_vgalcd_mst_axi4_s;            //write address of vgalcd_mst_axi4_s AXI bus AW channel
  input   [7:0]       awlen_vgalcd_mst_axi4_s;             //write length field of vgalcd_mst_axi4_s AXI bus AW channel
  input   [2:0]       awsize_vgalcd_mst_axi4_s;            //write size of vgalcd_mst_axi4_s AXI bus AW channel
  input   [1:0]       awburst_vgalcd_mst_axi4_s;           //write burst length of vgalcd_mst_axi4_s AXI bus AW channel
  input               awlock_vgalcd_mst_axi4_s;            //write lock of vgalcd_mst_axi4_s AXI bus AW channel
  input   [3:0]       awcache_vgalcd_mst_axi4_s;           //write cache field of vgalcd_mst_axi4_s AXI bus AW channel
  input   [2:0]       awprot_vgalcd_mst_axi4_s;            //write prot field of vgalcd_mst_axi4_s AXI bus AW channel
  input               awvalid_vgalcd_mst_axi4_s;           //write valid of vgalcd_mst_axi4_s AXI bus AW channel
  output              awready_vgalcd_mst_axi4_s;           //write ready of vgalcd_mst_axi4_s AXI bus AW channel

  //W Channel
  input   [63:0]      wdata_vgalcd_mst_axi4_s;             //write data of vgalcd_mst_axi4_s AXI bus W Channel
  input   [7:0]       wstrb_vgalcd_mst_axi4_s;             //write strobes of vgalcd_mst_axi4_s AXI bus W Channel
  input               wlast_vgalcd_mst_axi4_s;             //write last of vgalcd_mst_axi4_s AXI bus W Channel
  input               wvalid_vgalcd_mst_axi4_s;            //write valid of vgalcd_mst_axi4_s AXI bus W Channel
  output              wready_vgalcd_mst_axi4_s;            //write ready of vgalcd_mst_axi4_s AXI bus W Channel

  //B Channel
  output  [2:0]       bid_vgalcd_mst_axi4_s;               //b response id of vgalcd_mst_axi4_s AXI bus B Channel
  output  [1:0]       bresp_vgalcd_mst_axi4_s;             //b response status of vgalcd_mst_axi4_s AXI bus B Channel
  output              bvalid_vgalcd_mst_axi4_s;            //b response valid of vgalcd_mst_axi4_s AXI bus B Channel
  input               bready_vgalcd_mst_axi4_s;            //b response ready of vgalcd_mst_axi4_s AXI bus B Channel

  //AR Channel
  input   [2:0]       arid_vgalcd_mst_axi4_s;              //read id of vgalcd_mst_axi4_s AXI bus AR Channel
  input   [31:0]      araddr_vgalcd_mst_axi4_s;            //read address of vgalcd_mst_axi4_s AXI bus AR Channel
  input   [7:0]       arlen_vgalcd_mst_axi4_s;             //read length of vgalcd_mst_axi4_s AXI bus AR Channel
  input   [2:0]       arsize_vgalcd_mst_axi4_s;            //read size of vgalcd_mst_axi4_s AXI bus AR Channel
  input   [1:0]       arburst_vgalcd_mst_axi4_s;           //read burst length of vgalcd_mst_axi4_s AXI bus AR Channel
  input               arlock_vgalcd_mst_axi4_s;            //read lock of vgalcd_mst_axi4_s AXI bus AR Channel
  input   [3:0]       arcache_vgalcd_mst_axi4_s;           //read cache field of vgalcd_mst_axi4_s AXI bus AR Channel
  input   [2:0]       arprot_vgalcd_mst_axi4_s;            //read prot field of vgalcd_mst_axi4_s AXI bus AR Channel
  input               arvalid_vgalcd_mst_axi4_s;           //read valid of vgalcd_mst_axi4_s AXI bus AR Channel
  output              arready_vgalcd_mst_axi4_s;           //read ready of vgalcd_mst_axi4_s AXI bus AR Channel

  //R Channel
  output  [2:0]       rid_vgalcd_mst_axi4_s;               //read id of vgalcd_mst_axi4_s AXI bus R Channel
  output  [63:0]      rdata_vgalcd_mst_axi4_s;             //read data of vgalcd_mst_axi4_s AXI bus R Channel
  output  [1:0]       rresp_vgalcd_mst_axi4_s;             //read response status of vgalcd_mst_axi4_s AXI bus R Channel
  output              rlast_vgalcd_mst_axi4_s;             //read last of vgalcd_mst_axi4_s AXI bus R Channel
  output              rvalid_vgalcd_mst_axi4_s;            //read valid of vgalcd_mst_axi4_s AXI bus R Channel
  input               rready_vgalcd_mst_axi4_s;            //read ready of vgalcd_mst_axi4_s AXI bus R Channel

  //vgalcd_mst_axi4_m AXI bus


  //AW Channel
  output  [2:0]       awid_vgalcd_mst_axi4_m;              //write id of vgalcd_mst_axi4_m AXI bus AW channel
  output  [31:0]      awaddr_vgalcd_mst_axi4_m;            //write address of vgalcd_mst_axi4_m AXI bus AW channel
  output  [7:0]       awlen_vgalcd_mst_axi4_m;             //write length field of vgalcd_mst_axi4_m AXI bus AW channel
  output  [2:0]       awsize_vgalcd_mst_axi4_m;            //write size of vgalcd_mst_axi4_m AXI bus AW channel
  output  [1:0]       awburst_vgalcd_mst_axi4_m;           //write burst length of vgalcd_mst_axi4_m AXI bus AW channel
  output              awlock_vgalcd_mst_axi4_m;            //write lock of vgalcd_mst_axi4_m AXI bus AW channel
  output  [3:0]       awcache_vgalcd_mst_axi4_m;           //write cache field of vgalcd_mst_axi4_m AXI bus AW channel
  output  [2:0]       awprot_vgalcd_mst_axi4_m;            //write prot field of vgalcd_mst_axi4_m AXI bus AW channel
  output              awvalid_vgalcd_mst_axi4_m;           //write valid of vgalcd_mst_axi4_m AXI bus AW channel
  output  [3:0]       awvalid_vect_vgalcd_mst_axi4_m;      //write valid vector of vgalcd_mst_axi4_m AXI bus AW channel
  output  [3:0]       awregion_vgalcd_mst_axi4_m;          //write region selection signal
  input               awready_vgalcd_mst_axi4_m;           //write ready of vgalcd_mst_axi4_m AXI bus AW channel

  //W Channel
  output  [63:0]      wdata_vgalcd_mst_axi4_m;             //write data of vgalcd_mst_axi4_m AXI bus W Channel
  output  [7:0]       wstrb_vgalcd_mst_axi4_m;             //write strobes of vgalcd_mst_axi4_m AXI bus W Channel
  output              wlast_vgalcd_mst_axi4_m;             //write last of vgalcd_mst_axi4_m AXI bus W Channel
  output              wvalid_vgalcd_mst_axi4_m;            //write valid of vgalcd_mst_axi4_m AXI bus W Channel
  input               wready_vgalcd_mst_axi4_m;            //write ready of vgalcd_mst_axi4_m AXI bus W Channel

  //B Channel
  input   [2:0]       bid_vgalcd_mst_axi4_m;               //b response id of vgalcd_mst_axi4_m AXI bus B Channel
  input   [1:0]       bresp_vgalcd_mst_axi4_m;             //b response status of vgalcd_mst_axi4_m AXI bus B Channel
  input               bvalid_vgalcd_mst_axi4_m;            //b response valid of vgalcd_mst_axi4_m AXI bus B Channel
  output              bready_vgalcd_mst_axi4_m;            //b response ready of vgalcd_mst_axi4_m AXI bus B Channel

  //AR Channel
  output  [2:0]       arid_vgalcd_mst_axi4_m;              //read id of vgalcd_mst_axi4_m AXI bus AR Channel
  output  [31:0]      araddr_vgalcd_mst_axi4_m;            //read address of vgalcd_mst_axi4_m AXI bus AR Channel
  output  [7:0]       arlen_vgalcd_mst_axi4_m;             //read length of vgalcd_mst_axi4_m AXI bus AR Channel
  output  [2:0]       arsize_vgalcd_mst_axi4_m;            //read size of vgalcd_mst_axi4_m AXI bus AR Channel
  output  [1:0]       arburst_vgalcd_mst_axi4_m;           //read burst length of vgalcd_mst_axi4_m AXI bus AR Channel
  output              arlock_vgalcd_mst_axi4_m;            //read lock of vgalcd_mst_axi4_m AXI bus AR Channel
  output  [3:0]       arcache_vgalcd_mst_axi4_m;           //read cache field of vgalcd_mst_axi4_m AXI bus AR Channel
  output  [2:0]       arprot_vgalcd_mst_axi4_m;            //read prot field of vgalcd_mst_axi4_m AXI bus AR Channel
  output              arvalid_vgalcd_mst_axi4_m;           //read valid of vgalcd_mst_axi4_m AXI bus AR Channel
  output  [3:0]       arvalid_vect_vgalcd_mst_axi4_m;      //read valid vector of vgalcd_mst_axi4_m AXI bus AR Channel
  output  [3:0]       arregion_vgalcd_mst_axi4_m;          //read region selection signal
  input               arready_vgalcd_mst_axi4_m;           //read ready of vgalcd_mst_axi4_m AXI bus AR Channel

  //R Channel
  input   [2:0]       rid_vgalcd_mst_axi4_m;               //read id of vgalcd_mst_axi4_m AXI bus R Channel
  input   [63:0]      rdata_vgalcd_mst_axi4_m;             //read data of vgalcd_mst_axi4_m AXI bus R Channel
  input   [1:0]       rresp_vgalcd_mst_axi4_m;             //read response status of vgalcd_mst_axi4_m AXI bus R Channel
  input               rlast_vgalcd_mst_axi4_m;             //read last of vgalcd_mst_axi4_m AXI bus R Channel
  input               rvalid_vgalcd_mst_axi4_m;            //read valid of vgalcd_mst_axi4_m AXI bus R Channel
  output              rready_vgalcd_mst_axi4_m;            //read ready of vgalcd_mst_axi4_m AXI bus R Channel

  //Clock and reset signals
  input               aclk;                                //main clock
  input               aresetn;                             //main reset



  
  // ---------------------------------------------------------------------------
  // Internal signals
  // ---------------------------------------------------------------------------


  // AW Channel wires at slave_port
  wire           aw_slave_port_dst_valid;
  wire           aw_slave_port_dst_ready;
  wire           aw_slave_port_src_valid;
  wire           aw_slave_port_src_ready;

  wire [55:0]    aw_slave_port_src_data;     // concatenation of the inputs
  wire [55:0]    aw_slave_port_dst_data;     // concatenation of the registered inputs

  // AR Channel wires at slave_port
  wire           ar_slave_port_dst_valid;
  wire           ar_slave_port_dst_ready;
  wire           ar_slave_port_src_valid;
  wire           ar_slave_port_src_ready;

  wire [55:0]    ar_slave_port_src_data;     // concatenation of the inputs
  wire [55:0]    ar_slave_port_dst_data;     // concatenation of the registered inputs

  // W Channel wires at slave_port
  wire           w_slave_port_dst_valid;
  wire           w_slave_port_dst_ready;
  wire           w_slave_port_src_valid;
  wire           w_slave_port_src_ready;

  wire [72:0]    w_slave_port_src_data;     // concatenation of the inputs
  wire [72:0]    w_slave_port_dst_data;     // concatenation of the registered inputs

  // R Channel wires at slave_port
  wire [69:0]    r_slave_port_src_data;     // concatenation of the inputs
  wire [69:0]    r_slave_port_dst_data;     // concatenation of the registered inputs

  // B Channel wires at slave_port
  wire [4:0]     b_slave_port_src_data;     // concatenation of the inputs
  wire [4:0]     b_slave_port_dst_data;     // concatenation of the registered inputs

  wire                security0;
  wire                security3;
  wire                security2;
  wire [3:0]          awvalid_vect_vgalcd_mst_axi4_m;            //
  wire [3:0]          arvalid_vect_vgalcd_mst_axi4_m;            //
  wire [3:0]          arcache_int_vgalcd_mst_axi4_m;
  wire [3:0]          awcache_int_vgalcd_mst_axi4_m;
  wire [2:0]          arprot_int_vgalcd_mst_axi4_m;
  wire [2:0]          awprot_int_vgalcd_mst_axi4_m;
  wire                arready_int_m;
  wire                awready_int_m;
  wire                arvalid_int_m;
  wire                awvalid_int_m;
  wire                arready_int_s;
  wire                awready_int_s;
  wire                arvalid_int_s;
  wire                awvalid_int_s;
  wire [31:0]         awaddr_int_s;
  wire [31:0]         araddr_int_s;
  wire [31:0]         awaddr_int_m;
  wire [31:0]         araddr_int_m;
  wire                cds_aw_enable;
  wire                cds_ar_enable;
  wire                cds_w_enable;

  // ---------------------------------------------------------------------------
  //  start of code
  // ---------------------------------------------------------------------------


  // Fixed security targets
  assign security0 = 1'b0;
  assign security3 = 1'b0;
  assign security2 = 1'b0;

  // AxVALID and AxREADY assigns

  // Wiring of int signals
  assign arvalid_int_m = arvalid_int_s;
  assign awvalid_int_m = awvalid_int_s;

  assign arready_int_s = arready_int_m;
  assign awready_int_s = awready_int_m;



  // Wiring at master_port
  assign arvalid_vgalcd_mst_axi4_m = arvalid_int_m & cds_ar_enable;
  assign awvalid_vgalcd_mst_axi4_m = awvalid_int_m & cds_aw_enable;
  assign arready_int_m  = arready_vgalcd_mst_axi4_m & cds_ar_enable;
  assign awready_int_m  = awready_vgalcd_mst_axi4_m & cds_aw_enable;

  // Address assigns across decode block
  assign awaddr_int_m = awaddr_int_s;
  assign araddr_int_m = araddr_int_s;

  // Address assigns at master_port
  assign awaddr_vgalcd_mst_axi4_m = awaddr_int_m;
  assign araddr_vgalcd_mst_axi4_m = araddr_int_m;

  // Drive AxPROT bits to appropriate values
  assign arprot_vgalcd_mst_axi4_m[2] = arprot_int_vgalcd_mst_axi4_m[2];
  assign arprot_vgalcd_mst_axi4_m[1] = 1'b1;
  assign arprot_vgalcd_mst_axi4_m[0] = arprot_int_vgalcd_mst_axi4_m[0];

  assign awprot_vgalcd_mst_axi4_m[2] = awprot_int_vgalcd_mst_axi4_m[2];
  assign awprot_vgalcd_mst_axi4_m[1] = 1'b1;
  assign awprot_vgalcd_mst_axi4_m[0] = awprot_int_vgalcd_mst_axi4_m[0];

  //------------------------------------------------------------------------------
  // AW address decode
  //
  //------------------------------------------------------------------------------
  nic400_asib_vgalcd_mst_axi4_decode_ysyx_rv32 u_aw_add_decode
  (
    .addr_s                 (awaddr_int_s),
    .aregion_out            (awregion_vgalcd_mst_axi4_m),
    .security0              (security0),
    .security3              (security3),
    .security2              (security2),
    .aprot                  (awprot_vgalcd_mst_axi4_m[1]),
    .acache_in              (awcache_int_vgalcd_mst_axi4_m),
    .acache_out             (awcache_vgalcd_mst_axi4_m),
    .avalid_int             (awvalid_vect_vgalcd_mst_axi4_m)
  );

nic400_asib_vgalcd_mst_axi4_wr_ss_cdas_ysyx_rv32 u_asib_vgalcd_mst_axi4_wr_ss_cdas
  (
    .aw_enable              (cds_aw_enable),
    .wr_enable              (cds_w_enable),
    .asel                   (awvalid_vect_vgalcd_mst_axi4_m),
    .avalid                 (awvalid_int_m),
    .aready                 (awready_int_m),
    .wvalid                 (wvalid_vgalcd_mst_axi4_m),
    .wready                 (wready_vgalcd_mst_axi4_m),
    .wlast                  (wlast_vgalcd_mst_axi4_m),
    .resp_valid             (bvalid_vgalcd_mst_axi4_m),
    .resp_ready             (bready_vgalcd_mst_axi4_m),

    // Miscelaneous connections
    .aclk                   (aclk),
    .aresetn                (aresetn)
  );

  //------------------------------------------------------------------------------
  // AR address decode
  //
  //------------------------------------------------------------------------------

  nic400_asib_vgalcd_mst_axi4_decode_ysyx_rv32 u_ar_add_decode
  (
    .addr_s                 (araddr_int_s),
    .aregion_out            (arregion_vgalcd_mst_axi4_m),
    .security0              (security0),
    .security3              (security3),
    .security2              (security2),
    .aprot                  (arprot_vgalcd_mst_axi4_m[1]),
    .acache_in              (arcache_int_vgalcd_mst_axi4_m),
    .acache_out             (arcache_vgalcd_mst_axi4_m),
    .avalid_int             (arvalid_vect_vgalcd_mst_axi4_m)
  );

nic400_asib_vgalcd_mst_axi4_rd_ss_cdas_ysyx_rv32 u_asib_vgalcd_mst_axi4_rd_ss_cdas
  (
    .ar_enable              (cds_ar_enable),
    .asel                   (arvalid_vect_vgalcd_mst_axi4_m),
    .avalid                 (arvalid_int_m),
    .aready                 (arready_int_m),
    .resp_valid             (rvalid_vgalcd_mst_axi4_m),
    .resp_last              (rlast_vgalcd_mst_axi4_m),
    .resp_ready             (rready_vgalcd_mst_axi4_m),

    // Miscelaneous connections
    .aclk                   (aclk),
    .aresetn                (aresetn)
  );

  // ---------------------------------------------------------------------------
  // AW Channel timing block wiring at slave_port
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign aw_slave_port_src_data = {awid_vgalcd_mst_axi4_s,
          awaddr_vgalcd_mst_axi4_s,
          awlen_vgalcd_mst_axi4_s,
          awsize_vgalcd_mst_axi4_s,
          awburst_vgalcd_mst_axi4_s,
          awlock_vgalcd_mst_axi4_s,
          awcache_vgalcd_mst_axi4_s,
          awprot_vgalcd_mst_axi4_s};

  // expand the concatenated registered values to the slave port outputs
  assign {awid_vgalcd_mst_axi4_m,
          awaddr_int_s,
          awlen_vgalcd_mst_axi4_m,
          awsize_vgalcd_mst_axi4_m,
          awburst_vgalcd_mst_axi4_m,
          awlock_vgalcd_mst_axi4_m,
          awcache_int_vgalcd_mst_axi4_m,
          awprot_int_vgalcd_mst_axi4_m} = aw_slave_port_dst_data;



  assign awvalid_int_s = aw_slave_port_dst_valid;
  assign aw_slave_port_dst_ready = awready_int_s;

  assign aw_slave_port_src_valid = awvalid_vgalcd_mst_axi4_s;
  assign awready_vgalcd_mst_axi4_s = aw_slave_port_src_ready;

  // ---------------------------------------------------------------------------
  // AR Channel timing block wiring at slave_port
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign ar_slave_port_src_data = {arid_vgalcd_mst_axi4_s,
          araddr_vgalcd_mst_axi4_s,
          arlen_vgalcd_mst_axi4_s,
          arsize_vgalcd_mst_axi4_s,
          arburst_vgalcd_mst_axi4_s,
          arlock_vgalcd_mst_axi4_s,
          arcache_vgalcd_mst_axi4_s,
          arprot_vgalcd_mst_axi4_s};

  // expand the concatenated registered values to the slave port outputs
  assign {arid_vgalcd_mst_axi4_m,
          araddr_int_s,
          arlen_vgalcd_mst_axi4_m,
          arsize_vgalcd_mst_axi4_m,
          arburst_vgalcd_mst_axi4_m,
          arlock_vgalcd_mst_axi4_m,
          arcache_int_vgalcd_mst_axi4_m,
          arprot_int_vgalcd_mst_axi4_m} = ar_slave_port_dst_data;



  assign arvalid_int_s = ar_slave_port_dst_valid;
  assign ar_slave_port_dst_ready = arready_int_s;

  assign ar_slave_port_src_valid = arvalid_vgalcd_mst_axi4_s;
  assign arready_vgalcd_mst_axi4_s = ar_slave_port_src_ready;

  // ---------------------------------------------------------------------------
  // W Channel timing block wiring at slave_port
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign w_slave_port_src_data = {wdata_vgalcd_mst_axi4_s,
          wstrb_vgalcd_mst_axi4_s,
          wlast_vgalcd_mst_axi4_s};

  // expand the concatenated registered values to the slave port outputs
  assign {wdata_vgalcd_mst_axi4_m,
          wstrb_vgalcd_mst_axi4_m,
          wlast_vgalcd_mst_axi4_m} = w_slave_port_dst_data;



  assign wvalid_vgalcd_mst_axi4_m = w_slave_port_dst_valid;
  assign w_slave_port_dst_ready = wready_vgalcd_mst_axi4_m;

  assign w_slave_port_src_valid = wvalid_vgalcd_mst_axi4_s;
  assign wready_vgalcd_mst_axi4_s = w_slave_port_src_ready;

  // ---------------------------------------------------------------------------
  // R Channel timing block wiring at slave_port
  //
  // No register specified for R Channel: Wire straight across
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign r_slave_port_src_data = {rid_vgalcd_mst_axi4_m,
          rdata_vgalcd_mst_axi4_m,
          rresp_vgalcd_mst_axi4_m,
          rlast_vgalcd_mst_axi4_m};

  // expand the concatenated registered values to the slave port outputs
  assign {rid_vgalcd_mst_axi4_s,
          rdata_vgalcd_mst_axi4_s,
          rresp_vgalcd_mst_axi4_s,
          rlast_vgalcd_mst_axi4_s} = r_slave_port_dst_data;


  assign r_slave_port_dst_data = r_slave_port_src_data;

  assign rvalid_vgalcd_mst_axi4_s = rvalid_vgalcd_mst_axi4_m;
  assign rready_vgalcd_mst_axi4_m = rready_vgalcd_mst_axi4_s;

  // ---------------------------------------------------------------------------
  // B Channel timing block wiring at slave_port
  //
  // No register specified for B Channel: Wire straight across
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign b_slave_port_src_data = {bid_vgalcd_mst_axi4_m,
          bresp_vgalcd_mst_axi4_m};

  // expand the concatenated registered values to the slave port outputs
  assign {bid_vgalcd_mst_axi4_s,
          bresp_vgalcd_mst_axi4_s} = b_slave_port_dst_data;


  assign b_slave_port_dst_data = b_slave_port_src_data;

  assign bvalid_vgalcd_mst_axi4_s = bvalid_vgalcd_mst_axi4_m;
  assign bready_vgalcd_mst_axi4_m = bready_vgalcd_mst_axi4_s;

  // ---------------------------------------------------------------------------
  // Instantiation of Timing Isolation Blocks
  // ---------------------------------------------------------------------------

  //  AW Channel Timing Isolation Register Block on slave_port

  // HNDSHK_MODE = rev
  // PAYLOAD_WIDTH = 56
  nic400_asib_vgalcd_mst_axi4_chan_slice_ysyx_rv32
    #(
       `RS_REV_REG,  // Handshake Mode
       56  // Payload Width
     )
  u_aw_slave_port_chan_slice
    (
     // global interconnect inputs
     .aresetn               (aresetn),
     .aclk                  (aclk),
     // inputs
     .src_valid             (aw_slave_port_src_valid),
     .src_data              (aw_slave_port_src_data),
     .dst_ready             (aw_slave_port_dst_ready),

     // outputs
     .src_ready             (aw_slave_port_src_ready),
     .dst_data              (aw_slave_port_dst_data),
     .dst_valid             (aw_slave_port_dst_valid)
     );



  //  AR Channel Timing Isolation Register Block on slave_port

  // HNDSHK_MODE = rev
  // PAYLOAD_WIDTH = 56
  nic400_asib_vgalcd_mst_axi4_chan_slice_ysyx_rv32
    #(
       `RS_REV_REG,  // Handshake Mode
       56  // Payload Width
     )
  u_ar_slave_port_chan_slice
    (
     // global interconnect inputs
     .aresetn               (aresetn),
     .aclk                  (aclk),
     // inputs
     .src_valid             (ar_slave_port_src_valid),
     .src_data              (ar_slave_port_src_data),
     .dst_ready             (ar_slave_port_dst_ready),

     // outputs
     .src_ready             (ar_slave_port_src_ready),
     .dst_data              (ar_slave_port_dst_data),
     .dst_valid             (ar_slave_port_dst_valid)
     );



  //  W Channel Timing Isolation Register Block on slave_port

  // HNDSHK_MODE = rev
  // PAYLOAD_WIDTH = 73
  nic400_asib_vgalcd_mst_axi4_chan_slice_ysyx_rv32
    #(
       `RS_REV_REG,  // Handshake Mode
       73  // Payload Width
     )
  u_w_slave_port_chan_slice
    (
     // global interconnect inputs
     .aresetn               (aresetn),
     .aclk                  (aclk),
     // inputs
     .src_valid             (w_slave_port_src_valid),
     .src_data              (w_slave_port_src_data),
     .dst_ready             (w_slave_port_dst_ready),

     // outputs
     .src_ready             (w_slave_port_src_ready),
     .dst_data              (w_slave_port_dst_data),
     .dst_valid             (w_slave_port_dst_valid)
     );



  // R channel is set to wires at slave_port.

  // B channel is set to wires at slave_port.


  // ---------------------------------------------------------------------------



//  ==========================================================================
//  OVL Assertions
//  ==========================================================================
`ifdef ARM_ASSERT_ON

// Include Standard OVL Defines
`include "std_ovl_defines.h"




  //----------------------------------------------------------------------------
  // OVL_ASSERT: Ensure that AR valid vector is one hot when ARVALID
  //----------------------------------------------------------------------------
  // OVL_ASSERT_RTL
  assert_zero_one_hot
    #(`OVL_FATAL, 4, `OVL_ASSERT,
      "Error: AR Valid vector not one-hot zero")
      ovl_arvalid_vect_one_hot_zero
      (
        .clk (aclk),
        .reset_n (aresetn),
        .test_expr ( {4{arvalid_int_m}} & arvalid_vect_vgalcd_mst_axi4_m )
      );
  assert_never
    #(`OVL_FATAL, `OVL_ASSERT,
      "Error: AR Valid vector not one-hot during ARVALID")
      ovl_arvalid_vect_one_hot_when_arvalid
      (
        .clk (aclk),
        .reset_n (aresetn),
        .test_expr ( arvalid_int_m & ~|arvalid_vect_vgalcd_mst_axi4_m )
      );
  // OVL_ASSERT_END

  //----------------------------------------------------------------------------
  // OVL_ASSERT: Ensure that AW valid vector is one hot when AWVALID
  //----------------------------------------------------------------------------
  // OVL_ASSERT_RTL
  assert_zero_one_hot
    #(`OVL_FATAL, 4, `OVL_ASSERT,
      "Error: AW Valid vector not one-hot zero")
      ovl_awvalid_vect_one_hot_zero
      (
        .clk (aclk),
        .reset_n (aresetn),
        .test_expr ( {4{awvalid_int_m}} & awvalid_vect_vgalcd_mst_axi4_m )
      );
  assert_never
    #(`OVL_FATAL, `OVL_ASSERT,
      "Error: AW Valid vector not one-hot during AWVALID")
      ovl_awvalid_vect_one_hot_when_awvalid
      (
        .clk (aclk),
        .reset_n (aresetn),
        .test_expr ( awvalid_int_m & ~|awvalid_vect_vgalcd_mst_axi4_m )
      );
  // OVL_ASSERT_END


`endif
// ---------------------------------------------------------------------------


endmodule

`include "nic400_asib_vgalcd_mst_axi4_undefs_ysyx_rv32.v"



// --================================= End ===================================--
